Image Processing Implementation on FPGA Hardware with Mathematical Morphological Operators Centered in VHDL

Resumen: An image processing system implemented on a low range FPGA device is presented in this paper. The system is designed in VHDL. Mathematical morphological operators are implemented as a parallel process. An operator unit proposed is presented. The data flow management is detailed since the information in a row is processed at the same time. Also, an application example is presented. The system was applied to remove impulsive noise and to detect the gradient of an image. Furthermore, basic mathematical morphology concepts are illustrated.

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J. Carmona-Suárez, I. Santillan, S. Martínez-Díaz, J. L. Gómez-Torres & J.A.Sandoval-Galarza. Image Processing Implementation on FPGA Hardware with Mathematical Morphological Operators Centered in VHDL. Memorias del Congreso Nacional de Control Automático, pp. 466-470, 2018.

Palabras clave

Image Processing; Mathematical Morphology; FPGA; VHDL; Parallel Processing

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